Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;

Entity Exercise_4_13 IS
 Port(
  Din :  in std_logic_vector(6 downto 0); --7人表决信号输入，同意为‘1’，不同意为‘0’
  Red,Green: out std_logic      --表决通过绿指示灯亮，表决不通过红指示灯亮
  );
End Entity Exercise_4_13;

Architecture Art1 OF Exercise_4_13 IS
 Signal sum: integer range 0 to 7;
  Begin 
U1: Process(Din)
 Variable sum1,sum2:integer range 0 to 7;
 Begin
  case Din(6 downto 4) is
   when B"000" => sum1 := 0;
   when B"001" => sum1 := 1;
   when B"010" => sum1 := 1;
   when B"011" => sum1 := 2;
   when B"100" => sum1 := 1;
   when B"101" => sum1 := 2;
   when B"110" => sum1 := 2;
   when B"111" => sum1 := 3;
   when others => sum1 := 0;
  end case;
  
  case Din(3 downto 0) is
   when B"0000" => sum2 := 0;
   when B"0001" => sum2 := 1;
   when B"0010" => sum2 := 1;
   when B"0011" => sum2 := 2;
   when B"0100" => sum2 := 1;
   when B"0101" => sum2 := 2;
   when B"0110" => sum2 := 2;
   when B"0111" => sum2 := 3;
   when B"1000" => sum2 := 1;
   when B"1001" => sum2 := 2;
   when B"1010" => sum2 := 2;
   when B"1011" => sum2 := 3;
   when B"1100" => sum2 := 2;
   when B"1101" => sum2 := 3;
   when B"1110" => sum2 := 3;
   when B"1111" => sum2 := 4;
   when others  => sum2 := 0;
  end case;
    
  sum <= sum1 + sum2; 
   
 End Process U1;
 
 
U2: Process(sum)
 Begin
  if  sum >= 4 then
   Green <= '1';
   Red <= '0';
  else
   Green <= '0';
   Red <= '1'; 
  end if;
 End Process U2;

End Architecture Art1;

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