LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY Generic_Statement_02 IS  
 Generic ( msb_operand: INTEGER :=15; msb_sum: INTEGER :=15 );
 PORT( b: IN  std_logic_vector( msb_operand downto 0 ); 
   result: OUT std_logic_vector( msb_sum downto 0 ));
END;

ARCHITECTURE one OF Generic_Statement_02 IS

 COMPONENT addern
  PORT( a,b: IN  std_logic_vector; --注意矢量没有给出下标范围
    result: OUT std_logic_vector); 
 END COMPONENT;
 
 SIGNAL a: std_logic_vector( msb_sum /2 downto 0 );
 SIGNAL twoa: std_logic_vector( msb_operand downto 0 );

 BEGIN
  
  twoa <= a & a ;
  u1: addern PORT MAP ( a => twoa, b => b, result => result );
  u2: addern PORT MAP ( a => b( msb_operand downto msb_operand/2 + 1 ), b => b( msb_operand/2 downto 0 ), result => a );
END;

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