LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY Generic_Statement IS

 PORT( d1,d2,d3,d4,d5,d6,d7: IN  std_logic;
   q1,q2: OUT std_logic);
END;

ARCHITECTURE one OF Generic_Statement IS
 
 COMPONENT andn  --元件andn声明
  GENERIC ( n :integer );
  PORT( a: IN  std_logic_vector( n-1 downto 0);
    c: OUT std_logic);
 END COMPONENT;
 
 BEGIN
  u1: andn  GENERIC MAP ( n => 2 ) --类属映射语句，类属参量n被赋值为2。注意该行最后无标点符号
     PORT MAP ( a(0) => d1, a(1) => d2, c => q1 );
  u2: andn GENERIC MAP ( n => 5) --类属映射语句，类属参量n被赋值为5
     PORT MAP ( a(0) => d3, a(1) => d4, a(2) => d5, a(3) => d6, a(4) => d7, c => q2 );
     
END;

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