LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--USE ieee.std_logic_arith.ALL;
--USE ieee.std_logic_unsigned.ALL;
ENTITY FIFO IS
GENERIC ( n: POSITIVE := 8 ; -- Data width
m: POSITIVE := 18 ); -- Data depth
PORT ( Reset,RD,WR,clk : IN std_logic;
DataIn : IN std_logic_vector(n-1 downto 0);
DataOut : OUT std_logic_vector(n-1 downto 0);
Full,Empty: BUFFER std_logic );
END ENTITY;
ARCHITECTURE one OF FIFO IS
TYPE FIFO_array IS ARRAY (0 TO (m-1)) OF bit_vector((n-1) downto 0);
SIGNAL FIFO_memory: FIFO_array;
SIGNAL WR_Addr,RD_Addr,Offset: NATURAL RANGE 0 TO (m-1);
SIGNAL DataBuffer: bit_vector((n-1) downto 0);
BEGIN
DataOut <= To_Stdlogicvector(DataBuffer) WHEN RD = '1' ELSE
(others => 'Z');
Offset <= ( WR_Addr - RD_Addr) WHEN WR_Addr > RD_Addr ELSE
( m - ( RD_Addr - WR_Addr ) ) WHEN RD_Addr > WR_Addr ELSE
0;
Empty <= '1' WHEN ( Offset = 0 ) ELSE '0' ;
Full <= '1' WHEN ( Offset = (m-1) ) ELSE '0' ;
FIFO_Read: PROCESS BEGIN
WAIT UNTIL rising_edge(clk);
IF Reset = '1' THEN
RD_Addr <= 0;
DataBuffer <= (others => '0');
ELSIF ( RD = '1' AND Empty = '0') THEN
DataBuffer <= FIFO_memory(RD_Addr);
RD_Addr <= ( RD_Addr+1 )MOD m;
END IF;
END PROCESS FIFO_Read;
FIFO_Write: PROCESS BEGIN
WAIT UNTIL rising_edge(clk);
IF Reset = '1' THEN
WR_Addr <= 0;
ELSIF ( WR = '1' AND Full = '0') THEN
FIFO_memory(WR_Addr) <= To_Bitvector(DataIn);
WR_Addr <= ( WR_Addr+1 )MOD m;
END IF;
END PROCESS FIFO_Write;
END one;
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