Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;

Entity Exercise_4_13 IS
 Port(
  Din :  in std_logic_vector(6 downto 0); --7人表决信号输入，同意为‘1’，不同意为‘0’
  Red,Green: out std_logic      --表决通过绿指示灯亮，表决不通过红指示灯亮
  );
End Entity Exercise_4_13;

Architecture Art2 OF Exercise_4_13 IS
 Signal sum: integer range 0 to 7;
  Begin 
U1: Process(Din)
 Variable sum1:integer range 0 to 7;
 Begin
  sum1 := 0;
  
  if Din(0) = '1' then
   sum1 := sum1 + 1;
  else
   sum1 := sum1;
  end if;
  
  if Din(1) = '1' then
   sum1 := sum1 + 1;
  else
   sum1 := sum1;
  end if;
  
  if Din(2) = '1' then
   sum1 := sum1 + 1;
  else
   sum1 := sum1;
  end if;
  
  if Din(3) = '1' then
   sum1 := sum1 + 1;
  else
   sum1 := sum1;
  end if;
  
  if Din(4) = '1' then
   sum1 := sum1 + 1;
  else
   sum1 := sum1;
  end if;
  
  if Din(5) = '1' then
   sum1 := sum1 + 1;
  else
   sum1 := sum1;
  end if;
  
  if Din(6) = '1' then
   sum1 := sum1 + 1;
  else
   sum1 := sum1;
  end if;
  
  sum <= sum1;
  
 End Process U1;
 
 
U2: Process(sum)
 Begin
  if  sum >= 4 then
   Green <= '1';
   Red <= '0';
  else
   Green <= '0';
   Red <= '1'; 
  end if;
 End Process U2;

End Architecture Art2;

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